 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * SRAM based FPGA Dedicated to Space Use * SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the need for Triple Modular Redundancy (TMR) * Produced on Rad Hard 0.35m CMOS Process * Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series * High Performance - 46K Available ASIC gates (50% typ. routable) - 60 MHz Internal Performance - 20 MHz System Performance - 30 MHz Array Multipliers - 18 ns FreeRAMTM access time - Internal Tri-state Capability in Each Cell FreeRAM - 18432 Bits of Distributed SRAM Independent of Logic Cells - Flexible, Single/Dual Port, Synchronous/Asynchronous 32x4 RAM blocks 8 Global Clocks and 4 Additional Dedicated PCI Clocks - Fast, Low Skew Clock Distribution - Programmable Rising/Falling Edge Transitions - Distributed Clock Shutdown Capability for Low Power Management Global Reset Option 384 PCI Compliant I/Os - Programmable Output Drive - Fast, Flexible Array Access Facilitates Pin Locking Package Options - MQFPF160 - MQFPF256 Design Software (System Designer) - Combination of Atmel internally developed tools, and industry standard design tools - Fast and Efficient Synthesis - Efficient Integration (Libraries, Interface, Full Back-annotation) - Over 75 Automatic Component Generators Create Thousands of Speed and Area Optimized Logic and RAM Functions - Automatic/Interactive Multi-chip Partitioning Supply Voltage 3.3V AT40KFL040 is a 5V Tolerant Version No Single Event Latch-up below a LET Threshold of 70 MeV/mg/cm2 Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019 Quality Grades - QML -Q and -V with SMD 5962-03250 - ESCC with 9304/008 Design Kit (AT40KEL-DK) Including: - A Board with the RH FPGA (MQFPF160 or MQFPF256) - A configuration memory (AT17 Atmel EEPROM) - Design software and documentation - ISP cable and software Easy Migration to Atmel Gate Arrays for High Volume Production Note: All features and characteristics described for AT40KEL040 in this document, also apply to the AT40KFL040 unless specified otherwise. * * Rad Hard Reprogrammable FPGAs with FreeRAM * * * * AT40KEL040 AT40KFL040 * * * * * * * 4155I-AERO-06/06 *** Table 1. AT40KEL040 Device Available ASIC Gates (50% typ. routable) Rows x Columns Core Cells Registers RAM Bits I/O (max) AT40KEL040 46K 48 x 48 2,304 3,056 18,432 384 Description The AT40KEL040 is a fully PCI-compliant, SRAM-based FPGA with distributed 18 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and 46,000 ASIC gates. I/O counts range from 129 to 384 in Aerospace standard packages and support 3.3V. The AT40KFL040 is a 5V tolerant version. The AT40KEL040 is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used Windows (R) / Linux(R) platform. Atmel's design tools provide easy integration with industry standard tools such as Synplicity, Modelsim and Leonardo Spectrum/Precision Synthesis. See the IDS datasheet for other supported tools. The AT40KEL040 can be used as a co-processor for high-speed (DSP/processorbased) designs by implementing a variety of compute-intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications. The AT40KEL040 FPGA offers a patented distributed 18 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool. The AT40KEL040's patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KEL040's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. The AT40KEL040 is capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40KEL040 can act as a reconfigurable co-processor. The AT40KEL040 FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already Fast, Flexible and Efficient SRAM Fast, Efficient Array and Vector Multipliers Cache Logic Design Automatic Component Generators 2 AT40KEL040 4155I-AERO-06/06 AT40KEL040 proven functions. The Automatic Component Generators work seamlessly with industrystandard schematic and synthesis tools to create the fastest, most efficient designs available. The patented AT40KEL040 series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Devices offer 46,000 usable ASIC gates, and have 3,056 registers. AT40K series FPGAs utilize a reliable 0.35m single-poly, 4-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based integrated development system (IDS) is used to create AT40KEL040 series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell's small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. AT40KEL040 Configurator Statistics extracted from configuration bitstreams show that the maximum needed size is 1Mbit. In order to keep the maximum number of pins assigned to signals, it is recommended to use a serial configuration interface. This is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip. It is packaged into a 28-pin DIL Flat Pack 400mils wide. This memory has been tested for total dose under bias and unbiased conditions, exhibiting far better results when unbiased; this is the reason why it is recommended to switch off the memory when it is not in the configuration mode. In addition, heavy ions tests have shown that the data stored in the memory cells are not corrupted eventhough errors may be detected while downloading the bitstream; this is the result of the data serialization from the parallel memory plan; therefore, it is recommended to use the FPGA CRC while configuring it, and to resume the configuration when an error is detected. 3 4155I-AERO-06/06 The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure 2 on page 5). At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM(1), with either synchronous or asynchronous operation. Note: 1. The right-most column can only be used as single-port RAM. Figure 1. Symmetrical Array Surrounded by I/O = I/O Pad = AT40K Cell = Repeater Row = Repeater Column = FreeRAM Note: AT40K has registered I/Os. Group enable every sector for tri-states on obuf's. 4 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Figure 2. Floorplan (Representative Portion)(1) = Core Cell RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM Note: 1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool. 5 4155I-AERO-06/06 The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-bus segment spans eight cells and "leapfrogs" or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are implemented through pass gates in the cell-bus interface (see following page). Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resource on the AT40KEL040 is used as a dual-function resource. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40KEL040 software tools are designed to accommodate dual-function buses in an efficient manner. Table 2. Dual-function Buses Function Cell Output Enable RAM Output Enable RAM Write Enable RAM Address RAM Data In RAM Data Out Clocking Set/Reset Type Local Express Express Express Local Local Express Express Plane(s) 5 2 1 1-5 1 2 4 5 Direction Horizontal and Vertical Vertical Vertical Vertical Horizontal Horizontal Vertical Vertical Bus half length at array edge Bus half length at array edge Bus full length at array edge Bus in first column to left of RAM block Bus full length at array edge Bus in first column to left of RAM block Buses full length at array edge Buses in second column to left of RAM block Comments 6 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Figure 3. Busing Plane (One of Five) = AT40KEL040 AT40K/40KAL = Local/Local or Express/Express Turn Point = Row Repeater = Column Express Express bus bus Local bus 7 4155I-AERO-06/06 Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). Figure 4. Cell Connections CEL CEL CEL plane 5 plane 4 plane 3 plane 2 plane 1 WXYZL W X Y Z L plane 5 plane 4 plane 3 plane 2 plane 1 Horizontal busing plane CEL CEL CEL CEL Vertical busing plane Diagonal direct connect CEL CEL Orthogonal direct connect CEL (a) Cell-to-cell Connections (b) Cell-to-bus Connections 8 AT40KEL040 4155I-AERO-06/06 AT40KEL040 The Cell Figure 5 depicts the AT40KEL040 cell. Configuration bits for separate muxes and pass gates are independent. All permutations of programmable muxes and pass gates are legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let signals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. This allows bus signals to switch planes to achieve greater routability. Up to five simultaneous local/local turns are possible. The AT40KEL040 FPGA core cell is a highly configurable logic block based around two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the "front end" of the cell. This AND gate is an important feature in the implementation of efficient array multipliers. Figure 5. The Cell "1" NW NE SE SW "1" "1" N E S W X W Y Z FB X W Y 8X1 LUT 8X1 LUT OUT "0" "1" OUT "1" V1 H1 V2 H2 V3 H3 V4 H4 V5 H5 10 Z D Q CLOCK RESET/SET "1" OEH OEV L Pass gates X Y NW NE SE SW N E S W X = Diagonal Direct connect or Bus Y = Orthogonal Direct Connector Bus W = Bus Connection Z = Bus Connection FB = Internal Feed back With this functionality in each core cell, the core cell can be configured in several "modes". The core cell flexibility makes the AT40KEL040 architecture well suited to most digital design application areas (see Figure 6). 9 4155I-AERO-06/06 Figure 6. Some Single Cell Modes A B C D Synthesis Mode. This mode is particularly important for the use of VHDL design. VHDL Synthesis tools generally will produce as their output large amounts of random logic functions. Having a 4-input LUT structure gives efficient random logic optimization without the delays associated with larger LUT structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell. Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40KEL040 core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell. LUT DQ Q (Registered) and/or Q SUM LUT or DQ A B C LUT SUM (Registered) and/or CARRY LUT DSP/Multiplier Mode. This mode is used to efficiently DQ A B C D PRODUCT (Registered) implement array multipliers. An array multiplier is an array or of bitwise multipliers, each implemented as a full adder PRODUCT and/or LUT with an upstream AND gate. Using this AND gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the AT40K architecture. CARRY DQ Q and/or CARRY IN LUT Counter Mode. Counters are fundamental to almost all digital designs. They are the basis of state machines, timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit counter can be implemented in one core cell. Again, the output can be registered, tri-stated and/or fed back. LUT CARRY A B C EN Q Tri-state/Mux Mode. This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching. 10 AT40KEL040 4155I-AERO-06/06 2:1 MUX AT40KEL040 RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sector rows (plane 2). A 5-bit Input Address Bus connects to five vertical express buses in same column. A 5-bit Output Address Bus connects to five vertical express buses in same column. Ain (input address) and Aout (output address) alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to the vertical express buses in the same column. Figure 7. RAM Connections (One Ram Block) CLK CLK CLK CLK Din Ain Dout Aout 32 x 4 RAM CLK WEN OEN Reading and writing of the 18 ns 32 x 4 dual-port FreeRAM are independent of each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load is logic 0, data is latched. These latches are used to synchronize Write Adress, Write Enable Not, and Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0, 11 4155I-AERO-06/06 data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous RAM) or they both select "1" (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the "AT40K/40KAL Configuration Series" application note at www.atmel.com). Figure 8. RAM Logic CLOCK "1" 0 1 1 "1" 0 Ain 5 Load Read Address Aout 5 Load Latch Write Address WEN Load 32 x 4 Dual-port RAM Write Enable NOT "1" OE Latch Din 4 Load 4 Din Clear Latch Dout Dout RAM-Clear Byte Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KEL040's FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators. 12 AT40KEL040 4155I-AERO-06/06 4155I-AERO-06/06 2-to-4 Decoder WE Write Address 2-to-4 Decoder Read Address Dout(0) Dout(1) Dout(2) Dout(3) Din(0) Din(1) Din(2) Din(3) Din Din Aout WEN OEN WEN OEN Ain Ain Aout Dout Ain WEN OEN Aout Dout Din Dout Din Aout WEN OEN Dout Ain Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) Din(4) Dout(4) Dout(5) Dout(6) Dout(7) Din Ain Aout WEN OEN Ain WEN OEN Aout Dout Din Dout Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din(5) Din(6) Din(7) Local Buses Express Buses Dedicated Connections AT40KEL040 13 Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40KEL040 FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per edge column of the array for PCI specification. Even the derived clocks can be routed through the Global network. Access points are provided in the corners of the array to route the derived clocks into the global clock network. The IDS software tools handle derived clocks to global clock connections automatically if used. Each column of an array has a "Column Clock mux" and a "Sector Clock mux". The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to "0", using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus (see Figure 10 on page 15). The extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to provide fast clocking to right-side I/Os. The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant "0" is provided to each register's clock pins. After configuration on power-up, the registers either set or reset, depending on the user's choice. The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array. 14 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Figure 10. Clocking (for One Column of Cells) } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux "1" Sector Clock Mux Global Clock Line (Buried) Express Bus (Plane 4; Half length at edge) "1" Repeater Sector Clock Mux "1" "1" 15 4155I-AERO-06/06 Set/Reset Scheme The AT40KEL040 family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network. The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux (Figure 11 on page 17). The set/reset provided to each sector column of four cells is either inverted or non-inverted using the Sector Reset mux. The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up). 16 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Figure 11. Set/Reset (for One Column of Cells) Each Cell has a programmable Set or Reset Sector Set/Reset Mux Repeater "1" Global Set/Reset Line (Buried) "1" Express Bus (Plane 5; Half length at edge) "1" "1" Any User I/O can drive Global Set/Reset line 17 4155I-AERO-06/06 I/O Structure Pad AT40K has registered I/Os and group enable every sector for tri-states on obuf's. The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the device size and package. These unbonded I/Os are used to perform a variety of bus turns at the edge of the array. Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak "1" or "0" level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin. The input stage of each I/O cell has a number of parameters that can be programmed either as properties in schematic entry or in the I/O Pad Attributes editor in IDS. The threshold level is a CMOS-compatible level. A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative comparator circuit that adds 1V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. The input buffer can be programmed to include four different intrinsic delays as specified in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal. The output drive capabilities of each I/O are programmable. They can be set to FAST, MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability (16 mA at 3.3V) buffer and the fastest slew rate. MEDIUM produces a medium drive (12 mA at 3.3V) buffer, while SLOW yields a standard (4 mA at 3.3V) buffer. The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open drain (0 or Z) by programming an I/O's Source Selection mux. Of course, the output can be normal (0 or 1), as well. The Source Selection mux selects the source for the output signal of an I/O. See Figure 12 on page 21. The AT40KEL040 has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KEL040 has access to one Primary I/O and two Secondary I/Os. Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It also connects into the repeaters on the row immediately above and below the adjacent core cell. In addition, each Primary I/O also connects into the busing network of the three nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Primary I/O can be accessed from any logic cell on three separate rows or columns of the FPGA. See Figures 12a and 13a. Every logic cell at the edge of the FPGA array has two direct diagonal connections to a Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O Pull-up/Pull-down CMOS Schmitt Delays Drive Tri-State Source Selection Mux Primary, Secondary and Corner I/Os Primary I/O Secondary I/O 18 AT40KEL040 4155I-AERO-06/06 AT40KEL040 connects on the diagonal inputs to the cell above and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of the two nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Secondary I/O can be accessed from any logic cell on two rows or columns of the FPGA. See Figure 12a and Figure 13b. Corner I/O Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KEL040 FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array. This means that many different edge logic cells can access the Corner I/Os. See Figure 14. 19 4155I-AERO-06/06 Figure 12. South I/O (Mirrored for North I/O) TRI-STATE CELL "0" "1" VCC DRIVE PULL-UP "0" PAD "1" CELL PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY (a)(a) Primary I/O Primary I/O CELL TRI-STATE "0" "1" CELL VCC DRIVE PULL-UP "0" "1" PAD PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY CELL (b) Secondary I/O 20 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Figure 13. West I/O (Mirrored for East I/O) a. Primary I/0 TRI-STATE "0" "1" VCC PULL-UP "0" DRIVE CELL "1" PAD RST PULL-DOWN TTL/CMOS GND SCHMITT DELAY OCLK ICLK RST CELL b. Secondary I/O 21 4155I-AERO-06/06 Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) PULL-DOWN PULL-UP PAD PAD VCC VCC GND TTL/CMOS SCHMITT DELAY ICLK RST OCLK OCLK RST RST RST PULL-DOWN PULL-UP GND TTL/CMOS SCHMITT DELAY ICLK RST DRIVE TRI-ST ATE DRIVE TRI-ST ATE "0" "1" "0" "1" "0" TRI-STATE VCC PULL-UP DRIVE OCLK RST PAD "0" "1" "0" "1" "0" "1" CELL CELL PULL-DOWN TTL/CMOS SCHMITT DELAY GND ICLK RST "1" CELL 22 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125 C Storage Temperature ..................................... -65C to +150C Junction Temperature .................................................. +150C Voltage on Any Input Pin with Respect to Ground (1) ......-0.5V to 5.5V DC (KEL version) ................................................ -0.5V to 7.0V DC (KFL version) Voltage on Any Output Pin with Respect to Ground .................................-0.5V to 5.5V DC Supply Voltage (VCC) ...........................................-0.5V to 5.5V ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 4000V 1. For DC Input Voltage (VI) Minimum voltage of -0.5V DC, which may undershoot to -2.0V for pulses of less than 20 ns. *Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. DC and AC Operating Range Operating Temperature VCC Power Supply High (VIHC) Input Voltage Level (CMOS) Low (VILC) -55C to +125C 3.3V 0.3V 70% VCC to VCC + 0.3V DC (KEL version) 70% VCC to 5.5V DC (KFL version) -0.3V to 30% VCC DC 23 4155I-AERO-06/06 DC Characteristics Symbol VIH VIL Parameter High-level Input Voltage Low-level Input Voltage Conditions CMOS TTL CMOS TTL IOH = -4 mA VCC = 3.3V VOH High-level Output Voltage IOH = -12 mA VCC = 3.3V IOH = -16 mA VCC = 3.3V IOL = +4 mA VCC = 3.3V VOL Low-level Output Voltage IOL = +12 mA VCC = 3.3V IOL = +16 mA VCC = 3.3V IIH IIL High-level Input Current Low-level Input Current VIN = VCC max With pull-down, VIN = VCC VIN = VSS With pull-up, VIN = VSS Without pull-down, VOUT = VCC max With pull-down, VOUT = VCC max Without pull-up, VOUT = VSS With pull-up, VOUT = VSS for CON Standby, unprogrammed All pins -5 20 -5 -300.0 -5 20 -5 -500 -150.0 1 -110 5 10 -50 75 Min 70% VCC 2.0 -0.3 -0.3 2.4 2.4 2.4 0.4 0.4 0.4 5 300 5 -20 5 300 30% VCC 0.8 Typ Max Unit V V V V V V V V V V A A A A A A mA IOZH High-level Tri-state Output Leakage Current IOZL ICC CIN Note: Low-level Tri-state Output Leakage Current Standby Current Consumption Input Capacitance(1) A mA pF 1. Parameter based on characterization and simulation; it is not tested in production. Power-On Supply Requirements Atmel FPGAs require a minimum rated power supply current capacity to ensure proper initialization, and the power supply ramp-up time does not affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. Table 3. Power-on Supply Requirements Description Maximum Current(1)(2) Maximum Current Supply Note: 1.2 A 1. Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A larger capacity power supply may result in a larger initiallization current. 2. Ramp-up time is measured from 0V DC to 3.6V DC. Peak current required lasts less than 2 ms, and occurs near the internal power on reset threshold voltage. 24 AT40KEL040 4155I-AERO-06/06 AT40KEL040 AC Timing Characteristics Delays are based on fixed loads which are described in the notes. Maximum timing based on worst case: Vcc = 3.0V, temperature = 125C. Minimum timing based on best case: Vcc = 3.6V, temperature = -55C. Maximum delays are the average of tPDLH and tPDHL. Cell Function Core 2-input gate 3-input gate 3-input gate 4-input gate Fast carry Fast carry Fast crry Fast carry Fast carry Fast carry Fast carry Fast carry DFF DFF DFF DFF Incremental -> L Local output enable Local output enable tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) x/y -> x/y x/y/z -> x/y x/y/w -> x/y x/y/w/z -> x/y y -> y x -> y y -> x x -> x w -> y w -> x z -> y z -> x Clk -> x/y R -> x/y S -> x/y q -> w x/y -> L oe -> L oe -> L 2.9 3.1 3.5 3.5 2.8 2.6 2.8 2.9 3.5 3.5 3.1 3.0 4.3 4.1 2.8 4.3 2.5 2.9 0.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path Value Unit Notes AC Timing Characteristics All input I/O characteristics measured from VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD. All output I/O characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Repeaters Repeater Repeater Repeater Repeater Repeater Repeater tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) L -> E E -> E L -> L E -> L E -> IO L -> IO 1.3 1.3 1.3 1.3 0.7 0.7 ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path Value Unit Notes 25 4155I-AERO-06/06 Cell Function I/O Input Input Input Input Output, slow Output, medium Output, fast Output, slow Output, slow Output, medium Output, medium Output, fast Output, fast Parameter Path Value Unit Notes tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) tPZX (max) tPXZ (max) tPZX (max) tPXZ (max) pad -> x/y pad -> x/y pad -> x/y pad -> x/y x/y/E/L -> pad x/y/E/L -> pad x/y/E/L -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad 5.4 7.6 11.4 14.9 16.0 14.8 11.2 16.4 5.1 14.1 9.1 11.4 9.5 ns ns ns ns ns ns ns ns ns ns ns ns ns no extra delay 1 extra delay 2 extra delays 3 extra delays 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 26 AT40KEL040 4155I-AERO-06/06 AT40KEL040 AC Timing Characteristics Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum timings for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Global Clocks and Set/Reset GCK Input buffer FCK Input buffer Clock column driver Clock sector driver GSRN Input buffer Global clock to output tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) pad -> clock pad -> clock clock -> colclk colclk -> secclk colclk -> secclk clock pad -> out 3.3 1.9 1.7 0.8 10.3 21.3 ns ns ns ns ns ns rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load rising edge clock rising edge clock rising edge clock rising edge clock Parameter Path Value Unit Notes Fast clock to output tPD (max) clock pad -> out 19.9 ns Notes: 1. 2. 3. 4. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and simulation; not tested in production. Exact power calculation is available in Atmel FPGA Designer software. 27 4155I-AERO-06/06 AC Timing Characteristics Cell Function Asynchronous RAM Write Write Write Write Write Write Write Write Write/Read Read Read Read Synchronous RAM Write Write Write Write Write Write Write Write Write Write/Read Write/Read Read Read Read tCYC (min) tCLKL (min) tCLKH (min) tsetup (min) thold (min) tsetup (min) thold (min) tsetup (min) thold (min) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) cycle time clk clk we setup -> clk we hold -> clk wr addr setup -> clk wr addr hold -> clk wr data setup -> clk wr data hold -> clk din -> dout clk -> dout rd addr -> dout oe -> dout oe -> dout 28 6.5 6.5 5.0 0.0 6.5 0.0 5.1 0.0 14.1 7.9 13.1 4.5 4.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr rd addr = wr addr pulse width low pulse width high tWECYC (min) tWEL (min) tWEH (min) tsetup (min) thold (min) tsetup (min) thold (min) thold (min) tPD (max) tPD (max) tPZX (max) tPXZ (max) cycle time we we wr addr setup -> we wr addr hold -> we din setup -> we din hold -> we oe hold -> we din -> dout rd addr -> dout oe -> dout oe -> dout 28 6.5 6.5 7.0 0.0 6.5 0.0 0.0 14.1 13.1 4.5 4.5 ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr pulse width low pulse width high Parameter Path Value Unit Notes 28 AT40KEL040 4155I-AERO-06/06 AT40KEL040 FreeRAM Asynchronous Timing Characteristics Single Port Write/Read Dual Port Write with Read Dual Port Read 29 4155I-AERO-06/06 FreeRAM Synchronous Timing Characteristics Single Port Write/Read tCLKH CLK tWCS WE tACS ADDR 0 1 tWCH tACH 2 3 OE tOXZ DATA tDCS tDCH tOZX tAD Dual Port Write with Read tCYC tCLKH CLK tWCS WE tACS WR ADDR 0 1 tCLKL tWCH tACH 2 tDCS WR DATA tDCH RD ADDR = WR ADDR 1 tCD RD DATA 30 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Dual Port Read RD ADDR 0 1 OE tOZX tAD tOXZ DATA 31 4155I-AERO-06/06 Table 4. MQFP F-160 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal VCC I/O384_GCK8_A15 I/O383_A14 I/O382 I/O381 I/O372_A13 I/O371_A12 I/O370 I/O369 GND I/O360 I/O359 I/O348_A11 I/O347_A10 I/O344 I/O343 I/O338_A9 I/O337_A8 VCC GND I/O336_A7 I/O335_A6 I/O330 I/O329 I/O328 I/O326_A5 I/O325_A4 I/O314 I/O313 GND I/O304 I/O303 I/O298_A3 Pin Number 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Signal I/O297_CS1_A2 I/O292 I/O291 I/O290_GCK7_A1 I/O289_A0 GND TESTCLOCK VCC CCLK I/O288_GCK6 I/O287_D0 I/O286 I/O285 I/O278 I/O277_D1 I/O274 I/O273 GND I/O262_FCK4 I/O261 I/O260 I/O259_D2 I/O246 I/O245 I/O242_CHECK I/O241_D3 GND VCC I/O240 I/O239_D4 I/O236 I/O235 I/O222_CS0 I/O221_D5 Pin Number 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Signal I/O220 I/O219_FCK3 GND I/O208 I/O207 I/O206 I/O205_D6 I/O196 I/O195 I/O194_GCK5 I/O193_D7 RESETN VCC CON GND I/O192_GCK4 I/O191_D8 I/O190 I/O189 I/O184_D9 I/O183_D10 I/O180 I/O179 GND I/O168 I/O167 I/O166_D11 I/O165_D12 I/O152 I/O151 I/O146_D13 I/O145_D14 GND VCC 32 AT40KEL040 4155E-AERO-06/04 Pin Number 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Signal I/O144_INIT I/O143_D15 I/O138 I/O137 I/O124 I/O123 I/O122 I/O121 GND I/O110 I/O109 I/O102_LDC I/O101 I/O100 I/O99 I/O98_HDC I/O97_GCK3 M2 VCC M0 GND M1 I/O96_GCK2 I/O95_OTS I/O94 I/O93 I/O90 I/O89 I/O84 I/O83 GND I/O72_FCK2 I/O71 I/O70 Pin Number 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal I/O69 I/O54 I/O53 I/O50 I/O49 VCC GND I/O48_A23 I/O47_A22 I/O44 I/O43 I/O28_A21 I/O27_A20 I/O26 I/O25_FCK1 GND I/O16 I/O15 I/O6_A19 I/O5_A18 I/O4 I/O3 I/O2_A17 I/O1_GCLK1_A16 GND 33 AT40KEL040 4155E-AERO-06/04 Table 5. MQFP - F256 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal IO384_GCK8_A15 IO383_A14 IO382 IO381 IO378 IO377 GND VCC IO375 IO374 IO372_A13 IO371_A12 IO370 IO369 IO366 IO365 IO362 IO360 IO359 IO358 IO356 IO355 IO353 IO352 IO349 IO348_A11 IO347_A10 IO346 IO344 IO343 IO338_A9 IO337_A8 IO336_A7 Pin Number 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Signal IO335_A6 IO334 IO330 IO329 IO328 IO326_A5 IO325_A4 IO324 IO323 IO321 IO320 IO318 IO317 IO314 IO313 IO312 IO311 IO308 IO307 IO304 IO303 IO301 IO298_A3 GND VCC IO297_CS1_A2 IO291 IO292 IO290_GCK7_A1 IO289_A0 TESTCLOCK CCLK IO288_GCK6 IO287_D0 Pin Number 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Signal IO286 IO285 IO282 GND VCC IO278 IO277_D1 IO276 IO274 IO273 IO272 IO270 IO269 IO267 IO266 IO262_FCK4 IO261 IO260 IO259_D2 IO258 IO257 IO254 IO253 IO252 IO251 IO248 IO246 IO245 IO242_CHECK IO241_D3 IO240 IO239_D4 IO236 IO235 34 AT40KEL040 4155E-AERO-06/04 Pin Number 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Signal IO234 IO232 IO230 IO228 IO227 IO225 IO224 IO222_CS0 IO221_D5 IO220 IO219_FCK3 IO216 IO215 IO212 IO208 IO207 IO206 IO205_D6 IO204 GND VCC IO203 IO196 IO195 IO194_GCK5 IO193_D7 RESETN CON IO192_GCK4 IO191_D8 IO190 IO189 IO186 GND Pin Number 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 Signal VCC IO184_D9 IO183_D10 IO181 IO180 IO179 IO177 IO174 IO173 IO171 IO168 IO167 IO166_D11 IO165_D12 IO163 IO162 IO161 IO158 IO157 IO156 IO152 IO151 IO150 IO149 IO146_D13 IO145_D14 IO144_INIT IO143_D15 IO141 IO138 IO137 IO136 IO134 IO132 Pin Number 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 Signal IO131 IO129 IO128 IO124 IO123 IO122 IO121 IO120 IO119 IO116 IO115 IO113 IO110 IO109 IO101 GND VCC IO102_LDC IO99 IO100 IO98_HDC IO97_GCK3 M2 M0 M1 IO96_GCK2 IO95_OTS IO94 IO93 GND VCC IO90 IO89 IO86 35 AT40KEL040 4155E-AERO-06/04 Pin Number 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 Signal IO85 IO84 IO83 IO80 IO79 IO77 IO76 IO72_FCK2 IO71 IO70 IO69 IO67 IO66 IO63 IO62 IO60 IO59 IO57 IO56 IO54 IO53 IO50 IO49 IO48_A23 IO47_A22 IO44 IO43 IO41 IO39 IO36 IO35 IO34 IO33 IO30 Pin Number 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Signal IO29 IO28_A21 IO27_A20 IO26 IO25_FCK1 IO21 IO20 IO18 IO16 IO15 IO13 GND VCC IO6_A19 IO5_A18 IO4 IO3 IO2_A17 IO1_GCLK1_A16 36 AT40KEL040 4155E-AERO-06/04 AT40KEL040 Part/Package Availability and User I/O Counts (Including Dual-function Pins) Package MQFPF 160 MQFPF 256 AT40KEL040 129 233 37 4155I-AERO-06/06 Ordering Information Part Number AT40KEL040KW1-E 5962-0325001QXC 5962-0325001VXC 930400801 AT40KEL040KZ1-E 5962-0325001QYC 5962-0325001VYC 930400802 AT40KFL040KW1-E 5962-0325002QXC 5962-0325002VXC AT40KFL040KW1-SCC AT40KFL040KZ1-E 5962-0325002QYC 5962-0325002VYC AT40KFL040KZ1-SCC Package MQFPF160 MQFPF160 MQFPF160 MQFPF160 MQFPF256 MQFPF256 MQFPF256 MQFPF256 MQFPF160 MQFPF160 MQFPF160 MQFPF160 MQFPF256 MQFPF256 MQFPF256 MQFPF256 Version 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant 3.3V, 5V Tolerant Temperature Range 25C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C -55 to +125C -55 to +125C Quality Flow Engineering Samples QML Q QML V ESCC Engineering Samples QML Q QML V ESCC Engineering Samples QML Q QML V ESCC Engineering Samples QML Q QML V ESCC 38 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin - Front View 39 4155I-AERO-06/06 Multilayer Quad Flat Pack (MQFP) 256-pin - Front View 40 AT40KEL040 4155I-AERO-06/06 AT40KEL040 Datasheet Change Log Changes from 4155B 06/03 to 4155C 04/04 1. Addition of MQFP F256 package information 2. Pad/ Pin assignment updated. Table 4 on page 31. 3. Ordering information updated 4. Reference to design tools Changes from 4155C 06/03 to 4155D 04/04 Changes from 4155D 04/04 - to 4155E 06/04 Changes from 4155E 06/04 to 4155F 06/04 Changes from 4155F 06/04 to 4155G 05/05 Changes from 4155G 05/05 to 4155H 02/06 Changes from 4155H 02/06 to 4155I 06/06 1. Update of radiation hardness performance, page 1. 1. Updated FreeRAM timing characteristics, Section "FreeRAM Asynchronous Timing Characteristics", page 29. 1. Minor changes throughout the document. 1. Minor changes. 1. Added MQFP256 package. 1. Adding AT40KFL040 5V tolerant version. 2. Corrections on matrix decription. 41 4155I-AERO-06/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2006. All rights reserved. Atmel(R), logo and combinations thereof are registered trademarks, and Everywhere You Are(R) are the trade marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 4155I-AERO-06/06 |
Price & Availability of AT40KFL040
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |